The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to techniques for provision of core sparing on computing platforms that utilize multi-core processors.
To improve performance, some processors may include multiple processing cores. Each core may be assigned to perform a set of tasks. During operation, one of the cores may, however, encounter a fault condition, for example, due to damage or degradation of the circuitry within the core. Recovering from such errors may add latency and may further pose security issues when communicating with software elements external to the processor.